1. Field of the Invention
The present invention relates to a semiconductor memory device, such as a mask read only memory (ROM).
2. Description of Related Art
Known as a semiconductor memory device is, for example, a mask ROM. The mask ROM is a read only semiconductor memory device in which values to be stored are written in memory cells in a manufacturing process.
A read circuit of a conventional mask ROM will hereinafter be described with reference to FIG. 1.
A memory cell array 100 includes a plurality of memory cell transistors T11 to Tmn. The memory cell transistors T11 to Tmn have gates connected to word lines WL1 to WLm arranged in rows. The memory cell transistors T11 to Tmn also have drains connected to bit lines BL1 to BLn arranged in columns.
Some of the memory cell transistors T11 to Tmn have sources connected to a first voltage line which is at a ground voltage level (GND level), namely, grounded. The other memory cell transistors have sources which are in a floating state. In FIG. 1, the sources of the memory cell transistors T12, T1n, T21, Tm1 and Tmn are at the GND level, and the sources of the memory cell transistors T11, T22, T2n and Tm2 are in the floating state (denoted by a character F in this figure). Values to be stored are written according to the connection states of the sources of the corresponding memory cell transistors, namely, according to whether those sources are grounded or float.
For example, voltages to be read (also referred to hereinafter as “read voltages”) from the memory cell transistors T11 to Tmn may be set to a low level by grounding the sources of the memory cell transistors T11 to Tmn. On the contrary, the read voltages of the memory cell transistors T11 to Tmn may be set to a high level by allowing the sources of the memory cell transistors T11 to Tmn to float.
Selector circuits 110-1 to 110-n and precharge circuits 130-1 to 130-n are connected to the bit lines BL1 to BLn, respectively.
The selector circuits 110-1 to 110-n are composed of, for example, pMOS transistors (shortly referred to hereinafter as “pMOSs”) 122-1 to 122-n, respectively. The pMOSs 122-1 to 122-n have sources connected respectively to the bit lines BL1 to BLn and drains connected in common to a data line DL. When select signals (denoted by arrows S1-1 to S1-n in this figure) inputted respectively to the gates of the pMOSs 122-1 to 122-n are low in level, the pMOSs 122-1 to 122-n are turned on to electrically connect the bit lines BL1 to BLn with the data line DL, respectively. On the contrary, when the select signals S1-1 to S1-n are high in level, the pMOSs 122-1 to 122-n are turned off to electrically isolate the bit lines BL1 to BLn from the data line DL, respectively. In the following description, it is assumed that the selector circuits 110-1 to 110-n are turned on when the pMOSs 122-1 to 122-n thereof are turned on, and off when the pMOSs 122-1 to 122-n are turned off.
The precharge circuits 130-1 to 130-n include, for example, pMOSs 142-1 to 142-n and inverting circuits 144-1 to 144-n, respectively. The pMOSs 142-1 to 142-n have sources connected in common to a second voltage line which is at a supply voltage level (VDD level), and drains connected respectively to the bit lines BL1 to BLn. The select signals S1-1 to S1-n are inverted by the inverting circuits 144-1 to 144-n and then inputted to the gates of the pMOSs 142-1 to 142-n, respectively. As a result, when the select signals S1-1 to S1-n are high in level, the pMOSs 142-1 to 142-n are turned on to apply the supply voltage VDD to the bit lines BL1 to BLn, respectively, thereby causing the bit lines BL1 to BLn to assume the VDD level, or high level. On the other hand, when the select signals S1-1 to S1-n are low in level, the pMOSs 142-1 to 142-n are turned off. In the following description, it is assumed that the precharge circuits 130-1 to 130-n are turned on when the pMOSs 142-1 to 142-n thereof are turned on, and off when the pMOSs 142-1 to 142-n are turned off.
A read operation of the conventional mask ROM with the above-mentioned configuration will hereinafter be described with reference to FIGS. 2A to 2D.
In the initial state of every read cycle, all the select signals S1-1 to S1-n are set to a high level. At this time, the selector circuits 110-1 to 110-n are turned off, whereas the precharge circuits 130-1 to 130-n are turned on, so the bit lines BL1 to BLn assume the VDD level. Also, the word lines WL1 to WLm are set to the GND level, thereby causing all the memory cell transistors T11 to Tmn to be turned off.
A description will hereinafter be given of the case of reading a stored value of the memory cell transistor T11 set to a high-level read mode. For reading of the memory cell transistor T11, the bit line BL1 and the word line WL1 are selected.
When the bit line BL1 is selected, at a time t11, the select signal S1-1 becomes low in level and the other select signals S1-2 to S1-n are held at a high level. At this time, the precharge circuit 130-1 is turned off and the selector circuit 110-1 is turned on. As a result, the selected bit line (also referred to hereinafter as a “select bit line”) BL1 and the data line DL are electrically connected with each other, so as to have the same voltage level.
When the word line WL1 is selected, at a time t12, the selected word line WL1 is set to the VDD level, which is the level of a drive voltage of the memory cell transistor, and the other word lines WL2 to WLm are set to the GND level. If the word line WL1 becomes high in level, all the memory cell transistors T11 to Tin connected to the word line WL1 are turned on. In contrast, all the memory cell transistors T21 to Tmn connected to the other word lines WL2 to WLm remain off. Because the source of the memory cell transistor T11 is in the floating state, the bit line BL1 remains high in level although the memory cell transistor T11 is turned on. Accordingly, in a read period from the time t12 until a time t13, the voltage of the data line DL is VDD, so as to be outputted as a high-level signal (see FIG. 2A).
Next, a description will be given of the case of reading a stored value of the memory cell transistor T21 set to a low-level read mode. For reading of the memory cell transistor T21, the bit line BL1 and the word line WL2 are selected.
When the bit line BL1 is selected, at the time t11, the select signal S1-1 becomes low in level and the other select signals S1-2 to S1-n are held at a high level. At this time, the precharge circuit 130-1 is turned off and the selector circuit 110-1 is turned on. As a result, the selected bit line BL1 and the data line DL are electrically connected with each other, so as to have the same voltage level.
When the word line WL2 is selected, at the time t12, the selected word line WL2 is set to the VDD level and the other word lines WL1 and WL3 to WLm are set to the GND level. If the voltage of the word line WL2 is VDD, all the memory cell transistors T21 to T2n connected to the word line WL2 are turned on. In contrast, all the memory cell transistors T11 to T1n and T31 to Tmn connected to the other word lines WL1 and WL3 to WLm remain off. Because the source of the memory cell transistor T21 is grounded, the voltage of the bit line BL1 gradually falls due to through-current between the source and drain of the memory cell transistor T21 if the memory cell transistor T21 is turned on. As a result, in the read period from the time t12 until the time t13, the voltage of the data line DL, electrically connected with the bit line BL1, also gradually falls, so it is outputted as a low-level signal (see FIG. 2B).
Meanwhile, because the memory cell transistor T12 connected to the bit line (also referred to hereinafter as a “non-select bit line”) BL2, not selected when the memory cell transistor T11 is read, is turned on, through-current flows between the source and drain of the memory cell transistor T12, thereby causing charges stored on the bit line BL2 to be discharged to the first voltage line. At this time, since the select signal S1-2 is high in level, the precharge circuit 130-2 is turned on so as to supply current to the bit line BL2. As a result, the voltage of the bit line BL2 is stabilized at a value slightly lower than VDD (see FIG. 2C).
Also, when the memory cell transistor T21 is read, the bit line BL2 is held at VDD because the source of the memory cell transistor T22 is in the floating state although the memory cell transistor T22 is turned on (see FIG. 2D).
As aforementioned, in the read circuit of the conventional mask ROM, a non-select bit line is supplied with current by a corresponding precharge circuit, so that it is held at VDD or a value slightly lower than VDD, thereby making it possible to prevent the voltage of a select bit line from being reduced.
For example, when the memory cell transistor T11 is read, the memory cell transistor T12 is in its on state. For this reason, provided that no current is supplied to the bit line BL2 because the corresponding precharge circuit 130-2 is not provided, the voltage of the bit line BL2 will be reduced due to through-current between the source and drain of the memory cell transistor T12.
If the voltage of the bit line BL2 is reduced, the voltage of the bit line BL1 may be reduced by the action of coupling capacitance between the bit line BL1 and the bit line BL2. This reduction in the voltage of the bit line BL1 may result in misreading of the voltage of the bit line BL1, namely, the stored value of the memory cell transistor T11.
For this reason, the read circuit of the mask ROM holds the voltages of non-select bit lines at VDD or a value slightly lower than VDD using the precharge circuits 130-1 to 130-n. 
An example of the ROM read circuit is disclosed in Japanese Unexamined Patent Publication No. 2000-90685 (Patent Document 1).
However, in the above-mentioned conventional mask ROM read circuit, power consumption is increased because precharge circuits need to supply non-select bit lines with current during a reading period in order to prevent the voltage of the non-select bit lines from being reduced. Particularly, when there are a large number of bit lines, a big problem occurs in peak current in that through-currents flow through all memory cell transistors of the low-level read mode connected to a selected word line.
In addition, in large scale ROM, capacitance of bit lines becomes larger because length of bit lines becomes longer. Therefore, transition duration of bit lines during reading will increase. In other words, there is a problem that duration of reading bit lines becomes longer and reading speed of bit lines becomes slower.